Table of Contents

• Study of an Avalanche Compensation Mirror for SiGe High Performance Power Amplifiers Dedicated to 5G ApplicationsAnaïs Tourissaud, Eric Kerhervé, Nathalie Deltimple, Romain Mathieu. 1-6 [doi]
• Improving the Efficiency of Cryptography Algorithms on Resource-Constrained Embedded Systems via RISC-V Instruction Set ExtensionsCarlos Gabriel de Araujo Gewehr, Fernando Gehm Moraes. 1-6 [doi]
• Evaluation of Imprecise Subtractors into Test Zone Search for VVC EncodingRafael S. Ferreira, Luciano Agostini, Cláudio Machado Diniz, Bruno Zatt. 1-6 [doi]
• An UHD 4K@120fps Hardware for the VVC Prediction Refinement with Optical FlowMurilo R. Perleberg, Marcello M. Muñoz, Denis Maass, Vladimir Afonso, Luciano Agostini, Marcelo Schiavon Porto. 1-6 [doi]
• A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM ArchitecturesCleiton Magano Marques, Leonardo Heitich Brendler, Frédéric Wrobel, Alexandra L. Zimpeck, Walter E. Calienes Bartra, Paulo F. Butzen, Cristina Meinhardt. 1-6 [doi]
• Addressing Single-Event-Multiple-Transient Faults in Asynchronous RH-Click ControllersFelipe A. Kuentzer, Christos Georgakidis, Christos P. Sotiriou, Milos Krstic. 1-6 [doi]
• A 1.2 V, 80-230 MHz, 1.75 mW Phase Locked Loop N- Integer Clock SynthesizerMateus Castro, Leonardo Sulato de Moraes, Fabio Kelm Pereira, Eduardo Rodrigues de Lima. 1-5 [doi]
• A Non-Blocking Multistage Interconnection using Regular Clock Schemes for QCA CircuitsStefan T. Couperus Leal, Michael Canesche, Omar P. Vilela Neto, Ricardo S. Ferreira 0001, José A. M. Nacif. 1-6 [doi]
• Energy and Computing Assessment of Video Processing Kernels on CPU and FPGA platformsFillipi Mangrich, João Gabriel Firta Foes, Guilherme Correa, Ismael Seidel, Mateus Grellert. 1-6 [doi]
• Estimating Software and Hardware Video Decoder Energy Using Software Decoder ProfilingMatthias Kräanzler, André Kaup, Christian Herglotz. 1-6 [doi]
• Memory Controller with Adaptive ECC for Reliable System OperationMarco P. Stefani, César A. M. Marcon, Felipe G. A. e Silva, Jarbas Silveira. 1-6 [doi]
• FPGA Placement: Dynamic Decision Making Via Machine LearningTimothy Martin, Charlotte Barnes, Gary William Grewal, Shawki Areibi. 1-6 [doi]
• Evaluation and Comparison of Offset Compensation Techniques for a Multi-Stage ComparatorBeatriz E. H. Rezende, João L. J. Brum, Martina C. Rodrigues, Lucas Compassi Severo, Alessandro Gonçalves Girardi, William Prodanov, Paulo César Comassetto de Aguirre. 1-6 [doi]
• New Modified 4:2 Approximate Compressors for Low-Power ApplicationsVinicius Zanandrea, Cristina Meinhardt. 1-6 [doi]
• A Wireless Weatherproof Acoustic Sensor System to Detect Anomalies in Substation Power TransformersGabriel T. Gialluca, Gustavo T. Gialluca, Bruno Masiero, Eduardo Rodrigues de Lima, Larissa M. Almeida, Fabiano Fruett. 1-6 [doi]
• Power and Performance Costs of Radiation-Hardened ML Inference Models Running on Edge DevicesGeancarlo Abich, Anderson Ignacio da Silva, Jonas Gava, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis, Luciano Ost. 1-6 [doi]
• Design of an Advanced System-on-Chip Architecture for Chaotic Image EncryptionArthur Mendes Lima, Lucas Giovanni Nardo, Erivelton Geraldo Nepomuceno, Janier Arias-Garcia, Jones Yudi Mori. 1-6 [doi]
• Voltage Regulator with Ellipsoidal TransistorsM. P. Braga de Lima, Fernando A. P. Barúqui, Carlos Fernando Teodósio Soares. 1-4 [doi]
• Low-Energy and Reduced-Area Hardware Architecture for the Versatile Video Coding FMEVanio Rodrigues Filho, Ismael Seidel, Nicole Citadin, Marcio Monteiro, Mateus Grellert, José Luís Güntzel. 1-6 [doi]
• Exploring Nanomagnetic Logic with Bennett ClockingPedro Arthur R. L. Silva, Jeferson F. Chaves, José Augusto Miranda Nacif, Ricardo Ferreira, Omar Paranaiba Vilela Neto. 1-6 [doi]
• A 24.25-30.5GHz Fully Integrated SiGe Phase Shifter/VGA/Power Amplifier in 0.13µm BiCMOS Technology for 5G Beamforming ApplicationsAnaïs Tourissaud, Eric Kerhervé, Nathalie Deltimple, Steeven Voisin, Romain Mathieu. 1-6 [doi]
• ATMR design by construction based on two-level ALSGabriel Ammes, Guilherme B. Manske, Paulo F. Butzen, André Inácio Reis, Renato P. Ribas. 1-6 [doi]
• Design of Oscillator and Charge Pump for the Startup of Ultra-Low-Voltage Energy HarvestersFranciele Nornberg, Marcio Bender Machado, Rafael L. Radin, Carlos Galup-Montoro, Márcio C. Schneider. 1-5 [doi]
• Hardware Implementation of a Sliding Detection Algorithm for Robotic Hands Using Force SensorsJose Mendoza-Peñaloza, Daniel M. Muñoz. 1-6 [doi]
• 4K UHD@60fps Design For The VVC Affine Motion Estimation ReconstructorMarcello M. Muñoz, Denis Maass, Murilo R. Perleberg, Luciano Agostini, Guilherme Corrêa 0001, Marcelo Schiavon Porto. 1-6 [doi]
• A Hardware Design for the Multi-Transform Module of the Versatile Video Coding StandardBianca Silveira, Daniel Palomino 0001, Cláudio Machado Diniz, Guilherme Corrêa 0001. 1-6 [doi]
• Validating an Automated Asynchronous Synthesis Environment with a Challenging Design: RISC-VWillian Analdo Nunes, Marcos Luiggi Lemos Sartori, Matheus Trevisan Moreira, Fernando Gehm Moraes, Ney Laert Vilar Calazans. 1-6 [doi]
• AV1 Residual Syntax Elements Assessment and Efficient VLSI ArchitectureJiovana Sousa Gomes, Rodrigo N. Wuerdig, Fábio Luís Livi Ramos, Sergio Bampi. 1-6 [doi]
• FPGA-Based Brain-Computer Interface System for Real-Time Eye State ClassificationC. Acuña, C. Flores, Jimmy Tarrillo. 1-6 [doi]
• Towards a Machine Learning Based Method for Indirect Test Generation of Mixed-Signal CircuitsÁllan G. Ferreira, Lucas B. Zilch, Vinícius Navarro, Marcelo Soares Lubaszewski, Tiago R. Balen. 1-6 [doi]
• Jitter Noise Impact on Analog Spiking Neural Networks: STDP LimitationsZalfa Jouni, Theo P. Rioufol, Siqi Wang, Aziz Benlarbi-Delaï, Pietro M. Ferreira. 1-6 [doi]
• Revisiting the Ultra-Low Power Electronic Neuron Towards a Faithful Biomimetic BehaviorThéo Prats Rioufol, Zalfa Jouni, Thomas Soupizet, Pietro M. Ferreira. 1-6 [doi]
• An Energy-Efficient Interpolation Unit Targeting VVC Encoders with Approximate AdderRafael da Silva, Mateus Grellert, Ricardo Reis 0001. 1-5 [doi]
• A New Approach to Video Coding Leveraging Hybrid Coding and Video Frame InterpolationAndré Beims Bräscher, Gabriela Furtado Da Silveira, Luiz Henrique Cancellier, Ismael Seidel, Mateus Grellert, José Luís Güntzel. 1-6 [doi]
• Effect of Unique Table Implementation in the Performance of BDD PackagesJoao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis. 1-6 [doi]
• Secure Network Interface for Protecting IO Communication in Many-coresGustavo Comarú, Rafael Follmann Faccenda, Luciano Lores Caimi, Fernando Gehm Moraes. 1-6 [doi]
• Assessment of Lightweight Cryptography Algorithms on ARM Cortex-M ProcessorsNicolas Moura, Joaquim Lucena, Eduardo Pereira, Ney Calazans, Luciano Ost, Fernando Moraes 0001, Rafael Garibotti. 1-6 [doi]
• Implementation of Image Averaging on DRRA and DiMArch ArchitecturesPudi Dhilleswararao, Vamsi Goudu, Srinivas Boppu, Ritika Ratnu, Ahmed Hemani. 1-6 [doi]