A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR - researchr publication authors

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Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis. A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR. In 36th European Solid-State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, September 13-17, 2010. pages 422-425, IEEE, 2010. [doi]

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