A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR

Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis. A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR. In 36th European Solid-State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, September 13-17, 2010. pages 422-425, IEEE, 2010. [doi]

@inproceedings{ODonoghueHL10,
  title = {A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR},
  author = {Kerry A. O'Donoghue and Paul J. Hurst and Stephen H. Lewis},
  year = {2010},
  doi = {10.1109/ESSCIRC.2010.5619733},
  url = {https://doi.org/10.1109/ESSCIRC.2010.5619733},
  researchr = {https://researchr.org/publication/ODonoghueHL10},
  cites = {0},
  citedby = {0},
  pages = {422-425},
  booktitle = {36th European Solid-State Circuits Conference, ESSCIRC 2010, Sevilla, Spain, September 13-17, 2010},
  publisher = {IEEE},
  isbn = {978-1-4244-6662-7},
}