Tae-young Oh, Hoeju Chung, Jun-Young Park, Ki Won Lee, Seunghoon Oh, Su-Yeon Doo, Hyoung-Joo Kim, Changyong Lee, Hye-Ran Kim, Jong-Ho Lee, Jin-Il Lee, Kyung-Soo Ha, Young-Ryeol Choi, Young-Chul Cho, Yong-Cheol Bae, Taeseong Jang, Chulsung Park, Kwang-Il Park, Seong-Jin Jang, Joo-Sun Choi. A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation. J. Solid-State Circuits, 50(1):178-190, 2015. [doi]
@article{OhCPLODKLKLLHCCBJPPJC15,
title = {A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation},
author = {Tae-young Oh and Hoeju Chung and Jun-Young Park and Ki Won Lee and Seunghoon Oh and Su-Yeon Doo and Hyoung-Joo Kim and Changyong Lee and Hye-Ran Kim and Jong-Ho Lee and Jin-Il Lee and Kyung-Soo Ha and Young-Ryeol Choi and Young-Chul Cho and Yong-Cheol Bae and Taeseong Jang and Chulsung Park and Kwang-Il Park and Seong-Jin Jang and Joo-Sun Choi},
year = {2015},
doi = {10.1109/JSSC.2014.2353799},
url = {http://dx.doi.org/10.1109/JSSC.2014.2353799},
researchr = {https://researchr.org/publication/OhCPLODKLKLLHCCBJPPJC15},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {50},
number = {1},
pages = {178-190},
}