Hyunggoy Oh, Heetae Kim, Jaeil Lim, Sungho Kang. A selective error data capture method using on-chip DRAM for silicon debug of multi-core design. In International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017. pages 121-122, IEEE, 2017. [doi]
@inproceedings{OhKLK17-0,
title = {A selective error data capture method using on-chip DRAM for silicon debug of multi-core design},
author = {Hyunggoy Oh and Heetae Kim and Jaeil Lim and Sungho Kang},
year = {2017},
doi = {10.1109/ISOCC.2017.8368799},
url = {https://doi.org/10.1109/ISOCC.2017.8368799},
researchr = {https://researchr.org/publication/OhKLK17-0},
cites = {0},
citedby = {0},
pages = {121-122},
booktitle = {International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017},
publisher = {IEEE},
isbn = {978-1-5386-2285-8},
}