Daesun Oh, Keshab K. Parhi. Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes. In International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA. pages 1855-1858, IEEE, 2007. [doi]
@inproceedings{OhP07:0,
title = {Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check Codes},
author = {Daesun Oh and Keshab K. Parhi},
year = {2007},
doi = {10.1109/ISCAS.2007.378276},
url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2007.378276},
tags = {architecture},
researchr = {https://researchr.org/publication/OhP07%3A0},
cites = {0},
citedby = {0},
pages = {1855-1858},
booktitle = {International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA},
publisher = {IEEE},
}