A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara. A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. J. Solid-State Circuits, 42(4):820-829, 2007. [doi]

Authors

Shigeki Ohbayashi

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Makoto Yabuuchi

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Koji Nii

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Yasumasa Tsukamoto

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Susumu Imaoka

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Yuji Oda

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Tsutomu Yoshihara

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Motoshige Igarashi

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Masahiko Takeuchi

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Hiroshi Kawashima

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Yasuo Yamaguchi

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Kazuhiro Tsukamoto

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Masahide Inuishi

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Hiroshi Makino

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Koichiro Ishibashi

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Hirofumi Shinohara

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