A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability

Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara. A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. In Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan. pages 331-334, ACM, 2001. [doi]

@inproceedings{OhtakeNWF01,
  title = {A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability},
  author = {Satoshi Ohtake and Shintaro Nagai and Hiroki Wada and Hideo Fujiwara},
  year = {2001},
  doi = {10.1145/370155.370371},
  url = {http://doi.acm.org/10.1145/370155.370371},
  tags = {rule-based, completeness, testing},
  researchr = {https://researchr.org/publication/OhtakeNWF01},
  cites = {0},
  citedby = {0},
  pages = {331-334},
  booktitle = {Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
  publisher = {ACM},
  isbn = {0-7803-6634-4},
}