Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits

Takumi Okuhira, Tohru Ishihara. Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits. In José L. Ayala, Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, Gilles Sicard, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings. Volume 6951 of Lecture Notes in Computer Science, pages 237-246, Springer, 2011. [doi]

Authors

Takumi Okuhira

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Tohru Ishihara

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