Takumi Okuhira, Tohru Ishihara. Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits. In José L. Ayala, Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, Gilles Sicard, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings. Volume 6951 of Lecture Notes in Computer Science, pages 237-246, Springer, 2011. [doi]
@inproceedings{OkuhiraI11,
title = {Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits},
author = {Takumi Okuhira and Tohru Ishihara},
year = {2011},
doi = {10.1007/978-3-642-24154-3_24},
url = {http://dx.doi.org/10.1007/978-3-642-24154-3_24},
researchr = {https://researchr.org/publication/OkuhiraI11},
cites = {0},
citedby = {0},
pages = {237-246},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings},
editor = {José L. Ayala and Braulio García-Cámara and Manuel Prieto and Martino Ruggiero and Gilles Sicard},
volume = {6951},
series = {Lecture Notes in Computer Science},
publisher = {Springer},
isbn = {978-3-642-24153-6},
}