A simplified executable model to evaluate latency and throughput of networks-on-chip

Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi. A simplified executable model to evaluate latency and throughput of networks-on-chip. In Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta, editors, Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008. pages 170-175, ACM, 2008. [doi]

Abstract

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