Ari Paasio. Local memory and logic arrangement for ultra-low power array processors. In IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017. pages 1-4, IEEE, 2017. [doi]
@inproceedings{Paasio17,
title = {Local memory and logic arrangement for ultra-low power array processors},
author = {Ari Paasio},
year = {2017},
doi = {10.1109/ISCAS.2017.8050224},
url = {https://doi.org/10.1109/ISCAS.2017.8050224},
researchr = {https://researchr.org/publication/Paasio17},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017},
publisher = {IEEE},
isbn = {978-1-4673-6853-7},
}