Samuel N. Pagliarini, Dhiraj K. Pradhan. A placement strategy for reducing the effects of multiple faults in digital circuits. In 2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d'Aro, Girona, Spain, July 7-9, 2014. pages 69-74, IEEE, 2014. [doi]
@inproceedings{PagliariniP14,
title = {A placement strategy for reducing the effects of multiple faults in digital circuits},
author = {Samuel N. Pagliarini and Dhiraj K. Pradhan},
year = {2014},
doi = {10.1109/IOLTS.2014.6873674},
url = {http://dx.doi.org/10.1109/IOLTS.2014.6873674},
researchr = {https://researchr.org/publication/PagliariniP14},
cites = {0},
citedby = {0},
pages = {69-74},
booktitle = {2014 IEEE 20th International On-Line Testing Symposium, IOLTS 2014, Platja d'Aro, Girona, Spain, July 7-9, 2014},
publisher = {IEEE},
}