High performance bit-sliced pipelined comparator tree for FPGAs

Ayan Palchaudhuri, Anindya Sundar Dhar. High performance bit-sliced pipelined comparator tree for FPGAs. In 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016. pages 1-6, IEEE, 2016. [doi]

Authors

Ayan Palchaudhuri

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Anindya Sundar Dhar

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