Ayan Palchaudhuri, Anindya Sundar Dhar. High performance bit-sliced pipelined comparator tree for FPGAs. In 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016. pages 1-6, IEEE, 2016. [doi]
@inproceedings{PalchaudhuriD16-0,
title = {High performance bit-sliced pipelined comparator tree for FPGAs},
author = {Ayan Palchaudhuri and Anindya Sundar Dhar},
year = {2016},
doi = {10.1109/ISVDAT.2016.8064843},
url = {https://doi.org/10.1109/ISVDAT.2016.8064843},
researchr = {https://researchr.org/publication/PalchaudhuriD16-0},
cites = {0},
citedby = {0},
pages = {1-6},
booktitle = {20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016},
publisher = {IEEE},
isbn = {978-1-5090-1422-4},
}