Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier. Modeling of Crosstalk Fault in Defective Interconnects. In Johan Vounckx, Nadine Azémard, Philippe Maurine, editors, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings. Volume 4148 of Lecture Notes in Computer Science, pages 340-349, Springer, 2006. [doi]
Abstract is missing.