A 11 mW 68dB SFDR 100 MHz bandwidth ΔΣ-DAC based on a 5-bit 1GS/s core in 130nm

Pieter Palmers, Michiel Steyaert. A 11 mW 68dB SFDR 100 MHz bandwidth ΔΣ-DAC based on a 5-bit 1GS/s core in 130nm. In William Redman-White, Anthony J. Walton, editors, ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008. pages 214-217, IEEE, 2008. [doi]

@inproceedings{PalmersS08,
  title = {A 11 mW 68dB SFDR 100 MHz bandwidth ΔΣ-DAC based on a 5-bit 1GS/s core in 130nm},
  author = {Pieter Palmers and Michiel Steyaert},
  year = {2008},
  doi = {10.1109/ESSCIRC.2008.4681830},
  url = {https://doi.org/10.1109/ESSCIRC.2008.4681830},
  researchr = {https://researchr.org/publication/PalmersS08},
  cites = {0},
  citedby = {0},
  pages = {214-217},
  booktitle = {ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008},
  editor = {William Redman-White and Anthony J. Walton},
  publisher = {IEEE},
  isbn = {978-1-4244-2361-3},
}