Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits

Ashish Pancholy, Janusz Rajski, Larry J. McNaughton. Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. IEEE Design & Test of Computers, 9(1):72-83, 1992. [doi]

Abstract

Abstract is missing.