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Improving cache Performance Through Tiling and Data Alignment

Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau. Improving cache Performance Through Tiling and Data Alignment. In Gianfranco Bilardi, Afonso Ferreira, Reinhard Lüling, José D. P. Rolim, editors, Solving Irregularly Structured Problems in Parallel, 4th International Symposium, IRREGULAR 97, Paderborn, Germany, June 12-13, 1997, Proceedings. Volume 1253 of Lecture Notes in Computer Science, pages 167-185, Springer, 1997.

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