A shorted global clock design for multi-GHz 3D stacked chips

Liang-Teck Pang, Phillip J. Restle, Matthew R. Wordeman, Joel A. Silberman, Robert L. Franch, Gary W. Maier. A shorted global clock design for multi-GHz 3D stacked chips. In Symposium on VLSI Circuits, VLSIC 2012, Honolulu, HI, USA, June 13-15, 2012. pages 170-171, IEEE, 2012. [doi]

Authors

Liang-Teck Pang

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Phillip J. Restle

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Matthew R. Wordeman

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Joel A. Silberman

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Robert L. Franch

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Gary W. Maier

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