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Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Paolo Ienne. Improving FPGA Performance for Carry-Save Arithmetic. IEEE Trans. VLSI Syst., 18(4):578-590, 2010. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A novel FPGA logic block for improved arithmetic performanceHadi Parandeh-Afshar, Philip Brisk, Paolo Ienne. fpga 2008: 171-180 [doi] Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save ArithmeticAmit Verma, Ajay K. Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne. fpl 2010: 19-24 [doi]
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