Parth Parekh, Fei Yuan, Yushi Zhou. All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line. In 63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020, Springfield, MA, USA, August 9-12, 2020. pages 321-324, IEEE, 2020. [doi]
@inproceedings{ParekhYZ20a,
title = {All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line},
author = {Parth Parekh and Fei Yuan and Yushi Zhou},
year = {2020},
doi = {10.1109/MWSCAS48704.2020.9184630},
url = {https://doi.org/10.1109/MWSCAS48704.2020.9184630},
researchr = {https://researchr.org/publication/ParekhYZ20a},
cites = {0},
citedby = {0},
pages = {321-324},
booktitle = {63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020, Springfield, MA, USA, August 9-12, 2020},
publisher = {IEEE},
isbn = {978-1-7281-8058-8},
}