The following publications are possibly variants of this publication:
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- All-Digital ∆Σ TDC with Current-Starved Bi-Directional Gated Delay Line Time IntegratorFei Yuan, Parth Parekh. mwscas 2019: 493-496 [doi]
- All-digital ΔΣ TDC with differential bi-directional gated-delay-line time integratorYoung-Jun Park, Fei Yuan. mwscas 2017: 1513-1516 [doi]
- Low-power all-digital ΔΣ TDC with bi-directional gated delay line time integratorYoung-Jun Park, Fei Yuan. mwscas 2017: 679-682 [doi]
- Time-based all-digital Δ Σ time-to-digital converter with pre-skewed bi-directional gated delay line time integratorFei Yuan, Parth Parekh. iet-cds, 14(1):25-34, 2020. [doi]
- Gated Vernier Delay Line Time Integrator for Time-Mode Signal ProcessingParth Parekh, Fei Yuan 0005, Yushi Zhou. mwscas 2021: 1082-1085 [doi]
- Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converterParth Parekh, Fei Yuan 0005, Yushi Zhou. mj, 119:105316, 2022. [doi]
- Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time IntegratorParth Parekh, Fei Yuan. newcas 2018: 191-194 [doi]
- All-Digital Bi-Directional Gated Ring Oscillator Time Integrator for Mixed-Mode Signal ProcessingParth Parekh, Fei Yuan 0005, Yushi Zhou. newcas 2022: 25-29 [doi]
- All-Digital Time Integrator with Bi-Directional Gated Ring Oscillator / Shift RegisterFei Yuan. iscas 2023: 1-5 [doi]