Parth Parekh, Fei Yuan, Yushi Zhou. All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line. In 63rd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2020, Springfield, MA, USA, August 9-12, 2020. pages 321-324, IEEE, 2020. [doi]
Abstract is missing.