A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization

Myeong-Jae Park, Jinhyung Lee, Kyungjun Cho, Ji-Hwan Park, Junil Moon, Sung-Hak Lee, Tae-Kyun Kim, Sanghoon Oh, Seokwoo Choi, Yongsuk Choi, Ho Sung Cho, Tae Sik Yun, Young Jun Koo, Jae-Seung Lee, Byung Kuk Yoon, Young-Jun Park, Sangmuk Oh, Chang Kwon Lee, Seong-Hee Lee, Hyun Woo Kim, Yucheon Ju, Seung-Kyun Lim, Kyo Yun Lee, Sang-Hoon Lee, Woo Sung We, Seungchan Kim, Seung-Min Yang, Keonho Lee, In-Keun Kim, Younghyun Jeon, Jae Hyung Park, Jong-Chan Yun, Seonyeol Kim, Dong Yeol Lee, Su-Hyun Oh, Junghyun Shin, Yeonho Lee 0002, Jieun Jang, Joohwan Cho. A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. J. Solid-State Circuits, 58(1):256-269, 2023. [doi]

Abstract

Abstract is missing.