Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process

Eun-Bin Park, Taigon Song. Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process. IEEE Trans. VLSI Syst., 31(2):177-187, February 2023. [doi]

@article{ParkS23,
  title = {Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process},
  author = {Eun-Bin Park and Taigon Song},
  year = {2023},
  month = {February},
  doi = {10.1109/TVLSI.2022.3220339},
  url = {https://doi.org/10.1109/TVLSI.2022.3220339},
  researchr = {https://researchr.org/publication/ParkS23},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. VLSI Syst.},
  volume = {31},
  number = {2},
  pages = {177-187},
}