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Henry Park, Chih-Kong Ken Yang. In Situ SRAM Static Stability Estimation in 65-nm CMOS. J. Solid-State Circuits, 48(10):2541-2549, 2013. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A 2.74-pJ/bit, 17.7-Gb/s Iterative Concatenated-BCH Decoder in 65-nm CMOS for NAND Flash MemoryYoungjoo Lee, Hoyoung Yoo, Jaehwan Jung, Jihyuck Jo, In-Cheol Park. jssc, 48(10):2531-2540, 2013. [doi]
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