Young-Jun Park, Fei Yuan. Low-power all-digital ΔΣ TDC with bi-directional gated delay line time integrator. In IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017. pages 679-682, IEEE, 2017. [doi]
@inproceedings{ParkY17-5,
title = {Low-power all-digital ΔΣ TDC with bi-directional gated delay line time integrator},
author = {Young-Jun Park and Fei Yuan},
year = {2017},
doi = {10.1109/MWSCAS.2017.8053014},
url = {https://doi.org/10.1109/MWSCAS.2017.8053014},
researchr = {https://researchr.org/publication/ParkY17-5},
cites = {0},
citedby = {0},
pages = {679-682},
booktitle = {IEEE 60th International Midwest Symposium on Circuits and Systems, MWSCAS 2017, Boston, MA, USA, August 6-9, 2017},
publisher = {IEEE},
isbn = {978-1-5090-6389-5},
}