Deepchand Patel, Pravinkumar G. Parate, Prafulla S. Patil, S. Subbaraman. ASIC Implimentation of 1 Bit Full Adder. In First International Conference on Emerging Trends in Engineering and Technology, ICETET '08, Nagpur, Maharashtra, India, July 16-18, 2008. pages 463-467, IEEE Computer Society, 2008. [doi]
@inproceedings{PatelPPS08,
title = {ASIC Implimentation of 1 Bit Full Adder},
author = {Deepchand Patel and Pravinkumar G. Parate and Prafulla S. Patil and S. Subbaraman},
year = {2008},
doi = {10.1109/ICETET.2008.24},
url = {http://doi.ieeecomputersociety.org/10.1109/ICETET.2008.24},
researchr = {https://researchr.org/publication/PatelPPS08},
cites = {0},
citedby = {0},
pages = {463-467},
booktitle = {First International Conference on Emerging Trends in Engineering and Technology, ICETET '08, Nagpur, Maharashtra, India, July 16-18, 2008},
publisher = {IEEE Computer Society},
isbn = {978-0-7695-3267-7},
}