Parasitic-Aware Automatic Analog CMOS Circuit Design Environment

Subhash Jagadishchandra Patel, Rajesh A. Thakker. Parasitic-Aware Automatic Analog CMOS Circuit Design Environment. In 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019. pages 245-250, IEEE, 2019. [doi]

@inproceedings{PatelT19,
  title = {Parasitic-Aware Automatic Analog CMOS Circuit Design Environment},
  author = {Subhash Jagadishchandra Patel and Rajesh A. Thakker},
  year = {2019},
  doi = {10.1109/VLSID.2019.00061},
  url = {https://doi.org/10.1109/VLSID.2019.00061},
  researchr = {https://researchr.org/publication/PatelT19},
  cites = {0},
  citedby = {0},
  pages = {245-250},
  booktitle = {32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-0409-6},
}