Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis

Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu. Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. pages 80-85, IEEE, 2013. [doi]

Authors

Vinay C. Patil

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Sudarshan Srinivasan

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Wayne P. Burleson

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Sandip Kundu

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