Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu. Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. pages 80-85, IEEE, 2013. [doi]
Abstract is missing.