Vinay C. Patil, Sudarshan Srinivasan, Wayne P. Burleson, Sandip Kundu. Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis. In 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013. pages 80-85, IEEE, 2013. [doi]
@inproceedings{PatilSBK13,
title = {Impact of Clock-Gating on Power Distribution Network Using Wavelet Analysis},
author = {Vinay C. Patil and Sudarshan Srinivasan and Wayne P. Burleson and Sandip Kundu},
year = {2013},
doi = {10.1109/VLSID.2013.167},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2013.167},
researchr = {https://researchr.org/publication/PatilSBK13},
cites = {0},
citedby = {0},
pages = {80-85},
booktitle = {26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, Pune, India, January 5-10, 2013},
publisher = {IEEE},
isbn = {978-1-4673-4639-9},
}