Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors

Ayan Paul, Matt Amrein, Saket Gupta, Arvind Vinod, Abhishek Arun, Sachin S. Sapatnekar, Chris H. Kim. Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors. In Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012. pages 1-4, IEEE, 2012. [doi]

@inproceedings{PaulAGVASK12,
  title = {Staggered Core Activation: A circuit/architectural approach for mitigating resonant supply noise issues in multi-core multi-power domain processors},
  author = {Ayan Paul and Matt Amrein and Saket Gupta and Arvind Vinod and Abhishek Arun and Sachin S. Sapatnekar and Chris H. Kim},
  year = {2012},
  doi = {10.1109/CICC.2012.6330673},
  url = {http://dx.doi.org/10.1109/CICC.2012.6330673},
  researchr = {https://researchr.org/publication/PaulAGVASK12},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, CICC 2012, San Jose, CA, USA, September 9-12, 2012},
  publisher = {IEEE},
  isbn = {978-1-4673-1555-5},
}