A 4.8ps Resolution, PVT-insensitive Vernier-based TDC using switched-RO PLL and Back Gate Calibration - researchr publication authors

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Patroklos Pazionis, Andreas Tsimpos, Gerasimos Theodoratos, Georgios Panagopoulos. A 4.8ps Resolution, PVT-insensitive Vernier-based TDC using switched-RO PLL and Back Gate Calibration. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2025, Kalamata, Greece, July 6-9, 2025. pages 1-6, IEEE, 2025. [doi]

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