Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor

Martin J. Pearson, Chris Melhuish, Anthony G. Pipe, Mokhtar Nibouche, Ian Gilhespy, Kevin N. Gurney, Benjamin Mitchinson. Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor. In Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong, editors, Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005. pages 582-585, IEEE, 2005.

Authors

Martin J. Pearson

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Chris Melhuish

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Anthony G. Pipe

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Mokhtar Nibouche

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Ian Gilhespy

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Kevin N. Gurney

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Benjamin Mitchinson

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