Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors - researchr publication authors

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Volnei A. Pedroni, Ricardo P. Jasinski, Ricardo U. Pedroni. Panning sorter: A minimal-size architecture for hardware implementation of 2D Data Sorting Coprocessors. In 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2010, Kuala Lumpur, Malaysia, December 6-9, 2010. pages 923-926, IEEE, 2010. [doi]

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