J. C. Peña-Ramos, Ramon Parra-Michel. Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core. In Peter M. Athanas, Jürgen Becker, René Cumplido, editors, 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011. pages 375-379, IEEE Computer Society, 2011. [doi]
@inproceedings{Pena-RamosP11,
title = {Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core},
author = {J. C. Peña-Ramos and Ramon Parra-Michel},
year = {2011},
doi = {10.1109/ReConFig.2011.64},
url = {http://doi.ieeecomputersociety.org/10.1109/ReConFig.2011.64},
researchr = {https://researchr.org/publication/Pena-RamosP11},
cites = {0},
citedby = {0},
pages = {375-379},
booktitle = {2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011},
editor = {Peter M. Athanas and Jürgen Becker and René Cumplido},
publisher = {IEEE Computer Society},
isbn = {978-1-4577-1734-5},
}