Abstract is missing.
- An Analysis of Implanted Antennas in Xilinx FPGAsJacob Couch, Peter Athanas. 1-6 [doi]
- Adaptive Multi-client Network-on-Chip MemoryDiana Göhringer, Lukas Meder, Michael Hübner, Jürgen Becker. 7-12 [doi]
- FPGA Implementations of Radix-10 Digit Recurrence Fixed-Point and Floating-Point DividersMalte Baesler, Sven-Ole Voigt, Thomas Teufel. 13-19 [doi]
- Configuration Bitstream Reduction for SRAM-based FPGAs by Enumerating LUT Input PermutationsAmeer Abdelhadi, Guy G. F. Lemieux. 20-26 [doi]
- Empty Resource Compaction Algorithms for Real-Time Hardware Tasks Placement on Partially Reconfigurable FPGAs Subject to Fault OcurrenceXabier Iturbe, Khaled Benkrid, Tughrul Arslan, Chuan Hong, Imanol Martinez. 27-34 [doi]
- Resource Efficient Arithmetic Effects on RBM Neural Network Solution Quality Using MNISTAntony W. Savich, Medhat Moussa. 35-40 [doi]
- Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window DecompositionJeffrey B. Goeders, Guy G. F. Lemieux, Steven J. E. Wilton. 41-48 [doi]
- Object Recognition on a Chip: A Complete SURF-Based System on a Single FPGAMichael Schaeferling, Gundolf Kiefer. 49-54 [doi]
- Measuring and Predicting Temperature Distributions on FPGAs at Run-TimeMarkus Happe, Andreas Agne, Christian Plessl. 55-60 [doi]
- Heterogeneous Concurrent Error Detection (hCED) Based on Output AnticipationNaveed Imran, Ronald F. DeMara. 61-66 [doi]
- Configuring Field-Programmable Robot ArraysMark G. Arnold. 67-73 [doi]
- Identifying Merge-Beneficial Software Kernels for Hardware ImplementationAdriano K. Sanches, João M. P. Cardoso, Alexandre C. B. Delbem. 74-79 [doi]
- A Reconfigurable Computing System Based on a Cache-Coherent FabricNeal Oliver, Rahul R. Sharma, Stephen Chang, Bhushan Chitlur, Elkin Garcia, Joseph Grecco, Aaron Grier, Nelson Ijih, Yaping Liu, Pratik Marolia, Henry Mitchel, Suchit Subhaschandra, Arthur Sheiman, Tim Whisonant, Prabhat Gupta. 80-85 [doi]
- Multi-stream Regular Expression Matching on FPGAYun Qu, Yi-Hua E. Yang, Viktor K. Prasanna. 86-91 [doi]
- Characterizing Non-ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-Based ThermometersMoinuddin Sayed, Phillip H. Jones. 92-98 [doi]
- Design-for-Diversity for Improved Fault-Tolerance of TMR Systems on FPGAsRizwan Ashraf, Ouns Mouri, Rami Jadaa, Ronald F. DeMara. 99-104 [doi]
- An Architecture for Reconfigurable Multi-core ExplorationsOlivier Serres, Vikram K. Narayana, Tarek A. El-Ghazawi. 105-110 [doi]
- Using Self-Reconfiguration to Increase Manufacturing Yield of CNTFET-based ArchitecturesHui Zhu, Sébastien Le Beux, Nataliya Yakymets, Ian O'Connor. 111-116 [doi]
- Hardware OS Communication Service and Dynamic Memory Management for RSoCsSurya Narayanan, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis. 117-122 [doi]
- Dynamic Processor ReconfigurationMichael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker. 123-128 [doi]
- GIMME - A General Image Multiview Manipulation EngineCarl Ahlberg, Jörgen Lidholm, Fredrik Ekstrand, Giacomo Spampinato, Mikael Ekström, Lars Asplund. 129-134 [doi]
- Low-Cost TMR for Fault-Tolerance on Coarse-Grained Reconfigurable ArchitecturesThomas Schweizer, Philipp Schlicker, Sven Eisenhardt, Tommy Kuhn, Wolfgang Rosenstiel. 135-140 [doi]
- A PID Controller Applied to the Gain Control of a CMOS Camera Using Reconfigurable ComputingDrausio Linardi Rossi, Vanderlei Bonato, Eduardo Marques, João Miguel Gago Pontes de Brito Lima. 141-145 [doi]
- FPGA Based Acceleration of Decimal OperationsAlberto Nannarelli. 146-151 [doi]
- MiniMIPS: An 8-Bit MIPS in an FPGA for Educational PurposesCesar Ortega-Sanchez. 152-157 [doi]
- Linking Formal Description and Simulation of Runtime Reconfigurable SystemsThilo Pionteck, Christoph Osterloh, Carsten Albrecht. 158-163 [doi]
- Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware SystemsRuben Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo. 164-169 [doi]
- Optimizing Decomposition-Based Packet Classification Implementation on FPGAsLu Sun, Hoang Le, Viktor K. Prasanna. 170-175 [doi]
- Dynamic Constant Reconfiguration for Explicit Finite Difference Option PricingTobias Becker, Qiwei Jin, Wayne Luk, Stephen Weston. 176-181 [doi]
- Snake: An Efficient Strategy for the Reuse of Circuitry and Partial Computation Results in High-Performance Reconfigurable ComputingXabier Iturbe, Khaled Benkrid, Ali Ebrahim, Chuan Hong, Tughrul Arslan, Imanol Martinez. 182-189 [doi]
- A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in BioinformaticsPei Liu, Fatemeh O. Ebrahim, Ahmed Hemani, Kolin Paul. 190-197 [doi]
- An Integrated Prime-Field ECDLP Hardware Accelerator with High-Performance Modular Arithmetic UnitsSuvarna Mane, Lyndon Judge, Patrick Schaumont. 198-203 [doi]
- MicroECC: A Lightweight Reconfigurable Elliptic Curve Crypto-processorMichal Varchola, Tim Güneysu, Oliver Mischke. 204-210 [doi]
- dcTPM: A Generic Architecture for Dynamic Context ManagementThomas Feller, Sunil Malipatlolla, Michael Kasper, Sorin A. Huss. 211-216 [doi]
- A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA ImplementationsWei He, Eduardo de la Torre, Teresa Riesgo. 217-222 [doi]
- Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable FunctionYohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh. 223-228 [doi]
- Hardware Design of a 256-Bit Prime Field Multiplier Suitable for Computing Bilinear PairingsCuautëmoc Chävez Corona, Edgar Ferrer Moreno, Francisco Rodríguez-Henríquez. 229-234 [doi]
- Area-Efficient FPGA Implementations of the SHA-3 FinalistsBernhard Jungk, Jürgen Apfelbeck. 235-241 [doi]
- Efficient Hardware Accelerator for IPSec Based on Partial Reconfiguration on Xilinx FPGAsAhmad Salman, Marcin Rogawski, Jens-Peter Kaps. 242-248 [doi]
- Decrypting HDCP-protected Video Streams Using Reconfigurable HardwareBenno Lomb, Tim Güneysu. 249-254 [doi]
- Robustness Analysis of Different AES Implementations on SRAM Based FPGAsUli Kretzschmar, Armando Astarloa, Jesús Lázaro, Unai Bidarte, Jaime Jimenez. 255-260 [doi]
- Efficient Dual-Rail Implementations in FPGA Using Block RAMsShivam Bhasin, Sylvain Guilley, Youssef Souissi, Tarik Graba, Jean-Luc Danger. 261-267 [doi]
- Versatile FPGA Architecture for Skein Hashing AlgorithmDavid M. Webster, Marcin Lukowiak. 268-273 [doi]
- Enhancing the Randomness of a Combined True Random Number Generator Based on the Ring Oscillator Sampling MethodMieczyslaw Jessa, Lukasz Matuszewski. 274-279 [doi]
- RAM-Based Ultra-Lightweight FPGA Implementation of PRESENTElif Bilge Kavun, Tolga Yalçin. 280-285 [doi]
- A Simple Ethernet Stack Implementation in VHDL to Enable FPGA Logic ReconfigurabilityMarcus R. Perrett, Izzat Darwazeh. 286-290 [doi]
- FPGA-based CPG Robot Locomotion Modulation Using a Fuzzy Scheme and Visual InformationJose Hugo Barron-Zambrano, Cesar Torres-Huitzil, Jose Juan Garcia Hernandez. 291-296 [doi]
- Improving KLT in Embedded Systems by Processing Oversampling Video Sequence in Real-TimeZhiLei Chai, Jianbo Shi. 297-302 [doi]
- Architecture Based on Array Processors for Data-Dependent Superimposed Training Channel EstimationEduardo Romero-Aguirre, Ramon Parra-Michel, Roberto Carrasco-Alvarez, Aldo G. Orozco-Lugo. 303-308 [doi]
- Adaptive Energy-Efficient Architecture for WCDMA Channel EstimationZoltan Endre Rakosi, Zheng Wang, Anupam Chattopadhyay. 309-314 [doi]
- High-Speed Stochastic Processes Generator Based on Sum-of-Sinusoids for Channel EmulationL. R. Vela-Garcia, J. Vazquez Castillo, Ramon Parra-Michel, Alejandro Castillo Atoche. 315-320 [doi]
- Analysis of Parallel Sorting Algorithms in K-best Sphere-Decoder Architectures for MIMO SystemsPedro Cervantes Lozano, Luis Fernando González Pérez, Andrés David García García. 321-326 [doi]
- Fixed-Point CORDIC-Based QR Decomposition by Givens Rotations on FPGADongdong Chen, Mihai Sima. 327-332 [doi]
- Design and Implementation of a Simplified Turbo Decoder for 3GPP2Lennin C. Yllescas-Calderön, Adrian J. Espino-Orozco, Ramon Parra-Michel, Luis Fernando González Pérez. 333-338 [doi]
- Arbitrary Distribution Random Variable Generator for Channel EmulatorsR. Zarate-Martïnez, F. Peña-Campos, J. Vazquez Castillo, Ramon Parra-Michel. 339-344 [doi]
- Reconfigurable FPGA-Based Unit for Singular Value Decomposition of Large m x n MatricesLuis M. Ledesma-Carrillo, Eduardo Cabal-Yepez, René de Jesús Romero-Troncoso, Arturo Garcia-Perez, Roque Alfredo Osornio-Rios, Tobia D. Carozzi. 345-350 [doi]
- Reconfigurable Systems and Flexible Programming for Hardware Design, Verification and Software Enablement for System-on-a-Chip ArchitecturesJohn Aylward, Caterine H. Crawford, Ken Inoue, Scott Lekuch, Kay Müller, Mark Nutter, Hartmut Penner, Kai Schleupen, Jimi Xenidis. 351-356 [doi]
- Open-Scale: A Scalable, Open-Source NOC-based MPSoC for Design Space ExplorationRémi Busseuil, Lyonel Barthe, Gabriel Marchesan Almeida, Luciano Ost, Florent Bruguier, Gilles Sassatelli, Pascal Benoit, Michel Robert, Lionel Torres. 357-362 [doi]
- Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and ReconfigurationHamed Sajjadi Kia, Cristinel Ababei. 363-368 [doi]
- The Impact of Global Routing on the Performance of NoCs in FPGAsYe Lu, John V. McCanny, Sakir Sezer. 369-374 [doi]
- Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable CoreJ. C. Peña-Ramos, Ramon Parra-Michel. 375-379 [doi]
- FPGA Bootstrapping on PCIe Using Partial ReconfigurationPatrick S. Ostler, Michael J. Wirthlin, Joshua E. Jensen. 380-385 [doi]
- From Instruction Traces to Specialized Reconfigurable ArraysJoão Bispo, Nuno Paulino, João M. P. Cardoso, João Canas Ferreira. 386-391 [doi]
- Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor ArraysSrinivas Boppu, Frank Hannig, Jürgen Teich, Roberto Perez-Andrade. 392-397 [doi]
- A Self-Configuring TMR Scheme Utilizing Discrepancy ResolutionNaveed Imran, Ronald F. DeMara. 398-403 [doi]
- Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual VthKazuei Hironaka, Hideharu Amano. 404-409 [doi]
- Scalable Models for Autonomous Self-Assembled Reconfigurable SystemsTeresa Cervero, Sebastián López, Roberto Sarmiento, Tannous Frangieh, Peter Athanas. 410-415 [doi]
- Rainbow: An OS Extension for Hardware Multitasking on Dynamically Partially Reconfigurable FPGAsKrzysztof Jozwik, Hiroyuki Tomiyama, Masato Edahiro, Shinya Honda, Hiroaki Takada. 416-421 [doi]
- Improving FPGA Design and Evaluation Productivity with a Hardware Performance Monitoring InfrastructureAndrew G. Schmidt, Ron Sass. 422-427 [doi]
- Low-Power Reconfigurable Component Utilization in a High-Level Synthesis FlowDimitris Bekiaris, George Economakos, Efstathios Sotiriou-Xanthopoulos, Dimitrios Soudris. 428-433 [doi]
- RAP: More Efficient Memory Access in Highly Speculative Execution on Reconfigurable Adaptive ComputersBenjamin Thielmann, Thorsten Wink, Jens Huthmann, Andreas Koch 0001. 434-441 [doi]
- LiSARD: LabVIEW Integrated Softcore Architecture for Reconfigurable DevicesAlexander Pacholik, Johannes Klöckner, Marcus Müller, Irina Gushchina, Wolfgang Fengler. 442-447 [doi]
- EDA Environment for Evaluating a New Switch-Block-Free Reconfigurable ArchitectureMasatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka, Masayuki Sato, Takashi Ishiguro. 448-454 [doi]
- Automatic Type Inference for Resynthesis on Hardware Description LanguagesGerman Leon, Germán Fabregat, José M. Claver. 455-461 [doi]
- Enumeration of Costas Arrays Using GPUs and FPGAsRafael A. Arce-Nazario, José R. Ortiz-Ubarri. 462-467 [doi]
- An Energy Efficient FPGA Accelerator for Monte Carlo Option Pricing with the Heston ModelChristian de Schryver, Ivan Shcherbakov, Frank Kienle, Norbert Wehn, Henning Marxen, Anton Kostiuk, Ralf Korn. 468-474 [doi]
- Highly Parameterized K-means Clustering on FPGAs: Comparative Results with GPPs and GPUsHanaa M. Hussain, Khaled Benkrid, Ahmet T. Erdogan, Huseyin Seker. 475-480 [doi]
- GPU vs FPGA: Example Application on White Light InterferometryAlexander Pacholik, Marcus Müller, Wolfgang Fengler, Torsten Machleidt, Karl-Heinz Franke. 481-486 [doi]
- Spectral Method Characterization on FPGA and GPU AcceleratorsKarl Pereira, Peter Athanas, Heshan Lin, Wu Feng. 487-492 [doi]
- Digital Talking Book Player for the Visually Impaired Using FPGAsAzadeh Nazemi, Cesar Ortega-Sanchez, Iain Murray. 493-496 [doi]
- Performance-Area Improvement by Partial Reconfiguration for an Aerospace Remote Sensing ApplicationL. A. Cardona, J. Agrawal, Y. Guo, J. Oliver, C. Ferrer. 497-500 [doi]
- Toward All Optical Interconnections in Chip Multiprocessor (2)Malèk Channoufi, Pierre Lecoy, Rabah Attia, Bruno Delacressonniere, S. Garcia. 501-504 [doi]
- Techniques for Dynamically Mapping Computations to CoprocessorsJoão Bispo, João M. P. Cardoso. 505-508 [doi]
- Reconfigurable Block Floating Point Processing Elements in Virtex PlatformsGuillermo Conde, Gregory W. Donohoe. 509-512 [doi]