Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core

J. C. Peña-Ramos, Ramon Parra-Michel. Network on Chip Architectures for High Performance Digital Signal Processing Using a Configurable Core. In Peter M. Athanas, Jürgen Becker, René Cumplido, editors, 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011. pages 375-379, IEEE Computer Society, 2011. [doi]