Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs - researchr publication authors

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Pierre-Yves Peneau, Rabab Bouziane, Abdoulayse Gamatié, Erven Rohou, Florent Bruguier, Gilles Sassatelli, Lionel Torres, Sophiane Senni. Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs. In 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016. pages 162-169, IEEE, 2016. [doi]

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