Table of Contents

• Performance estimation of program partitions on multi-core platformsMalgorzata Michalska, J. J. Ahmad, Endri Bezati, Simone Casale Brunet, Marco Mattavelli. 1-8 [doi]
• Pipelining for dual supply voltagesTeng Xu 0001, Miodrag Potkonjak. 9-16 [doi]
• Thermally-aware composite run-time CPU power modelsMatthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Domenico Balsamo, Geoff V. Merrett, Bashir M. Al-Hashimi. 17-24 [doi]
• Investigation of electrical and thermal properties of carbon nanotube interconnectsAida Todri-Sanial. 25-32 [doi]
• Multi-scale electrothermal simulation and modelling of resistive random access memory devicesToufik Sadi, Liping Wang, Asen Asenov. 33-37 [doi]
• Thermoelectric effects in graphene and graphene-based nanostructures using atomistic simulationPhilippe Dollfus, V. Hung Nguyen, V. Truong Tran, M. Chung Nguyen, Arnaud Bournel, Jerome Saint-Martin. 38-43 [doi]
• Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computingJun Shiomi, Tohru Ishihara, Hidetoshi Onodera. 44-49 [doi]
• Hold-time violation analysis and fixing in near-threshold regionMohammad Saber Golanbari, Saman Kiamehr, Mehdi Baradaran Tahoori. 50-55 [doi]
• Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystemJames Myers, Pranay Prabhat, Anand Savanth, Sheng Yang, Rohan Gaddh. 56-63 [doi]
• Throughput balancing for energy efficient near-threshold manycoresIoannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano. 64-69 [doi]
• CMOS process transient noise simulation analysis and benchmarkingThomas Noulis. 70-75 [doi]
• Secure cryptographic hardware implementation issues for high-performance applicationsErica Tena-Sanchez, Antonio J. Acosta, Juan Núñez. 76-83 [doi]
• Coarse-grained learning-based dynamic voltage frequency scaling for video decodingJia Guo, Miodrag Potkonjak. 84-91 [doi]
• TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAsMuhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peeter Ellervee. 92-99 [doi]
• Deduplication in resistive content addressable memory based solid state driveR. Kaplan, Leonid Yavits, Amir Morad, Ran Ginosar. 100-106 [doi]
• Leakage current analysis in static CMOS logic gates for a transistor network design approachJorge Tonfat, Guilherme Flach, Ricardo Reis. 107-113 [doi]
• Run-time schedulability check of real-time tasks for energy efficiencyParham Haririan, Alberto García Ortiz. 114-119 [doi]
• Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuitsHossein Aghababa, Mohammadreza Kolahdouz, Behjat Forouzandeh. 120-127 [doi]
• Multiscale modeling of electron-ion interactions for engineering novel electronic devices and materialsLuca Larcher, Francesco Maria Puglisi, Andrea Padovani, Luca Vandelli, Paolo Pavan. 128-132 [doi]
• Optimized few layer graphene for heat spreadingSebastian Volz, Haoxue Han. 133-135 [doi]
• Design and verification of analog CMOS circuits using the gm/ID-method with age-dependent degradation effectsTheodor Hillebrand, Timur Schafer, Nico Hellwege, Marco Erstling, Dagmar Peters-Drolshagen, Steffen Paul. 136-141 [doi]
• RRAM variability and its mitigation schemesPeyman Pouyan, Esteve Amat, Said Hamdioui, Antonio Rubio. 141-146 [doi]
• A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effectsGeorgia Psychou, Tobias Gemmeke, Tobias G. Noll. 147-154 [doi]
• Investigating PVT variability effects on full addersStephanie O. Ames, Vinicius Zanandrea, Ingrid F. V. Oliveira, Samuel P. Toledo, Cristina Meinhardt. 155-161 [doi]
• Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffsPierre-Yves Peneau, Rabab Bouziane, Abdoulayse Gamatié, Erven Rohou, Florent Bruguier, Gilles Sassatelli, Lionel Torres, Sophiane Senni. 162-169 [doi]
• Securing embedded systems and their IPs with digital reconfigurable PUFsJason Xin Zheng, Teng Xu 0001, Miodrag Potkonjak. 169-176 [doi]
• Energy efficiency of 2-step charging power-clock for adiabatic logicHimadri Singh Raghav, Vivian A. Bartlett, Izzet Kale. 176-182 [doi]
• A software framework to calculate local temperatures in CMOS processorsAlireza Rohani, Hassan Ebrahimi, Hans G. Kerkhoff. 183-188 [doi]
• Subthreshold-based m-sequence code generator for ultra low-power body sensor nodesAhmad N. Abdulfattah, Charalampos C. Tsimenidis, Alex Yakovlev. 189-195 [doi]
• Novel memristive logic architecturesXiaohan Yang, Adedotun Adeyemo, Anu Bala, Abusaleh M. Jabir. 196-199 [doi]
• Using Iddt current degradation to monitor ageing in CMOS circuitsRadi Husin Bin Ramlee, Mark Zwolinski. 200-204 [doi]
• PMHLS 2.0: An automated optimization of power management during high-level synthesisDominik Macko. 205-212 [doi]
• Enabling environmentally-powered indoor sensor networks with dynamic routing and operationJia Guo, Teng Xu, Theano Stavrinos, Miodrag Potkonjak. 213-220 [doi]
• Automatic design of arbitrary-size approximate sorting networks with error guaranteeVojtech Mrazek, Zdenek Vasícek. 221-228 [doi]
• Comparison of low-voltage scaling in synchronous and asynchronous FD-SOI circuitsThiago Ferreira de Paiva Leite, Rodrigo Possamai Bastos, Rodrigo Iga Jadue, Laurent Fesquet. 229-234 [doi]
• Green metadata based adaptive DVFS for energy efficient video decodingYahia Benmoussa, Eric Senn, Nicolas Derouineau, Nicolas Tizon, Jalil Boukhobza. 235-242 [doi]
• Pushing minimum energy limits by optimal asymmetrical back plane biasing in 28 nm UTBB FD-SOIFrancisco Veirano, Lirida A. B. Naviner, Fernando Silveira. 243-249 [doi]
• Physical description and analysis of doped carbon nanotube interconnectsJie Liang, Liuyang Zhang, Nadine Azémard-Crestani, Pascal Nouet, Aida Todri-Sanial. 250-255 [doi]
• Impact of pipeline in the power performance of tunnel transistor circuitsMaria J. Avedillo, Juan Núñez. 256-261 [doi]
• Energy modeling of coupled interconnects including intrinsic misalignment effectsAmir Najafi, Lennart Bamberg, Ardalan Najafi, Alberto García Ortiz. 262-267 [doi]
• A novel leakage power reduction technique for nano-scaled CMOS digital integrated circuitsHossein Aghababa, Mohammadreza Kolahdouz. 268-274 [doi]
• Energy profile analysis of Zynq-7000 programmable SoC for embedded medical processing: Study on ECG arrhythmia detectionKonstantinos Railis, Vasileios Tsoutsouras, Sotirios Xydis, Dimitrios Soudris. 275-282 [doi]
• A new bank sensitive DRAMPower model for efficient design space explorationMatthias Jung 0001, Deepak M. Mathew, Éder F. Zulian, Christian Weis, Norbert Wehn. 283-288 [doi]
• The long way to power efficient, high performance DRAMsKlaus Hofmann, Tu Darmstadt. 289-290 [doi]
• Document classification systems in heterogeneous computing environmentsNasibeh Nasiri, Philip Colangelo, Oren Segal, Martin Margala, Wim Vanderbauwhede. 291-295 [doi]
• Multiscale modeling of electron-ion interactions for engineering novel electronic devices and materialsLuca Larcher, Francesco Maria Puglisi, Andrea Padovani, Luca Vandelli, Paolo Pavan. 296-300 [doi]
• Optimized few layer graphene for heat spreadingSebastian Volz, Haoxue Han. 301-303 [doi]