Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera. Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing. In 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016. pages 44-49, IEEE, 2016. [doi]
Abstract is missing.