Pierre-Yves Peneau, Rabab Bouziane, Abdoulayse Gamatié, Erven Rohou, Florent Bruguier, Gilles Sassatelli, Lionel Torres, Sophiane Senni. Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs. In 26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016. pages 162-169, IEEE, 2016. [doi]
@inproceedings{PeneauBGRBSTS16,
title = {Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs},
author = {Pierre-Yves Peneau and Rabab Bouziane and Abdoulayse Gamatié and Erven Rohou and Florent Bruguier and Gilles Sassatelli and Lionel Torres and Sophiane Senni},
year = {2016},
doi = {10.1109/PATMOS.2016.7833682},
url = {http://dx.doi.org/10.1109/PATMOS.2016.7833682},
researchr = {https://researchr.org/publication/PeneauBGRBSTS16},
cites = {0},
citedby = {0},
pages = {162-169},
booktitle = {26th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2016, Bremen, Germany, September 21-23, 2016},
publisher = {IEEE},
isbn = {978-1-5090-0733-2},
}