Parallel transistor level full-chip circuit simulation

He Peng, Chung-Kuan Cheng. Parallel transistor level full-chip circuit simulation. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009. pages 304-307, IEEE, 2009. [doi]

Authors

He Peng

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Chung-Kuan Cheng

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