He Peng, Chung-Kuan Cheng. Parallel transistor level full-chip circuit simulation. In Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009. pages 304-307, IEEE, 2009. [doi]
@inproceedings{PengC09-0,
title = {Parallel transistor level full-chip circuit simulation},
author = {He Peng and Chung-Kuan Cheng},
year = {2009},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=5090609&arnumber=5090677&count=326&index=63},
researchr = {https://researchr.org/publication/PengC09-0},
cites = {0},
citedby = {0},
pages = {304-307},
booktitle = {Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009},
publisher = {IEEE},
}