High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers

Chih-Chen Peng, Jau-Ji Jou, Tien-Tsorng Shih, Chien-Liang Chiu. High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers. In International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017. pages 182-183, IEEE, 2017. [doi]

@inproceedings{PengJSC17,
  title = {High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers},
  author = {Chih-Chen Peng and Jau-Ji Jou and Tien-Tsorng Shih and Chien-Liang Chiu},
  year = {2017},
  doi = {10.1109/ISOCC.2017.8368880},
  url = {https://doi.org/10.1109/ISOCC.2017.8368880},
  researchr = {https://researchr.org/publication/PengJSC17},
  cites = {0},
  citedby = {0},
  pages = {182-183},
  booktitle = {International SoC Design Conference, ISOCC 2017, Seoul, Korea (South), November 5-8, 2017},
  publisher = {IEEE},
  isbn = {978-1-5386-2285-8},
}