Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator - researchr publication authors

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Chih-Hsiang Peng, Po-Chuan Lin, Shovan Barma, Jhing-Fa Wang, Hong-Yuan Peng, K. Bharanitharan, Ta-Wen Kuan. Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator. IET Computers & Digital Techniques, 9(2):93-100, 2015. [doi]

This author has not been identified. Look up 'Chih-Hsiang Peng' in GoogleThis author has not been identified. Look up 'Po-Chuan Lin' in GoogleThis author has not been identified. Look up 'Shovan Barma' in GoogleThis author has not been identified. Look up 'Jhing-Fa Wang' in GoogleThis author has not been identified. Look up 'Hong-Yuan Peng' in GoogleThis author has not been identified. Look up 'K. Bharanitharan' in GoogleThis author has not been identified. Look up 'Ta-Wen Kuan' in Google

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