Chih-Hsiang Peng, Po-Chuan Lin, Shovan Barma, Jhing-Fa Wang, Hong-Yuan Peng, K. Bharanitharan, Ta-Wen Kuan. Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator. IET Computers & Digital Techniques, 9(2):93-100, 2015. [doi]
@article{PengLBWPBK15,
title = {Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator},
author = {Chih-Hsiang Peng and Po-Chuan Lin and Shovan Barma and Jhing-Fa Wang and Hong-Yuan Peng and K. Bharanitharan and Ta-Wen Kuan},
year = {2015},
doi = {10.1049/iet-cdt.2013.0153},
url = {http://dx.doi.org/10.1049/iet-cdt.2013.0153},
researchr = {https://researchr.org/publication/PengLBWPBK15},
cites = {0},
citedby = {0},
journal = {IET Computers & Digital Techniques},
volume = {9},
number = {2},
pages = {93-100},
}