Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology

Song Peng, Rajit Manohar. Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. In Gang Qu, Yehea I. Ismail, Narayanan Vijaykrishnan, Hai Zhou, editors, Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30 - May 1, 2006. pages 159-164, ACM, 2006. [doi]

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